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About PLL Frequency Synthesizers
PLL frequency synthesizers are electronic devices that produce frequencies coherent to a reference frequency. They use phase-locked loops (PLLs), electronic circuits that consist of a phase/frequency detector (PFD), low pass filter, and voltage-controlled oscillator (VCO). PLL frequency synthesizers use the PFD to compare a feedback frequency with a divided-down version of the reference frequency. Integral PLL frequency synthesizers divide the output frequency by an integer. Fractional PLL frequency synthesizers divide the output frequency by a non-integer. With both types of devices, the PFD’s output (current pulses) are filtered and integrated to generate a voltage. In turn, this voltage drives the VCO to increase or decrease the output frequency, moving the PFD’s average output towards zero. Sensitivity varies over the full VCO frequency range. Input reference counters are used to reduce the reference input frequency. Feedback counters are used to reduce the output frequency for comparison with the scaled reference frequency. Applications for PLL frequency synthesizers include wireless base stations, mobile hand sets, personal digital assistants (PDAs), broadband wireless access, satellite communications, and local area networks (LANs).
Selecting PLL frequency synthesizers requires an analysis of performance specifications such as frequency range, step size, settling time, output power, and voltage standing wave ratio (VSWR) vs. return loss. Frequency range is the range of frequencies that PLL frequency synthesizers can generate. Step size is the minimum output frequency that devices can achieve. Settling time is the maximum amount of time needed for the output signal to reach its final, stable state. Output power is usually measured in decibels per meter (dBm) for a 50 W load. Additional considerations include phase noise, reference spurs, and lock time. Phase noise is the ratio of the carrier power to the power found in a 1 Hz bandwidth at a defined frequency, usually 1 kHz. Reference spurs are artifacts at discrete offset frequencies generated by internal counters and charge pump operation at the PFD frequency. Lock time is the time needed to jump from one specified frequency to another specified frequency within a given frequency tolerance.
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M2077: Programming Guide Integer N PLL Synthesizer 35 - 2500 MHz
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M2076: Programming Guide Integer N PLL Synthesizer 35 - 1100 MHz
M/A-COM's surface mount frequency synthesizers integrate a low noise buffered VCO, phase locked loop circuit and low pass loop filter. The VCO output is coupled into the PLL circuit where the VCO...(read more)
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Engineering Web: PLL Frequency Synthesizers
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Analog Devices, Inc. | Converters Amplifiers Processors... PLL Synthesizers/VCOs Audio D/A Converters PLL Synthesizers/VCOs RF / IF Amplifiers See Analog Devices, Inc. Information |
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Application Note 1052 Noise Floor Measurement of PLL Frequency... The frequency tector is multiplied up by a factor of N, and appears inside the switching time and the suppression of reference spurs are loop of the See National Semiconductor Information |
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New Ultra-Small Dual PLL Frequency Synthesizer from Fujitsu :... supply pins ? VRF and VIF ? compared with four pins in other PLL frequency synthesizers, thus reducing the number of external parts required. See Fujitsu Limited Information |
Part Numbers for PLL Frequency Synthesizers
| Part # | Distributor | Manufacturer | Product Category | Description |
|---|---|---|---|---|
| RF PLL FREQUENCY SYNTHESIZER | Mectronic | ADF4112BRUZ-REEL7 | Not Provided | ADF4112BRUZ-REEL7 |
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